project c190


Nand2Tetris / Memory and Sequential Logic 03 May 2023 ➤ NAND2TETRIS PROJECT 03 Concept Notes A combinational circuit is one whose output does not depend on the value of the previous output, whereas a sequential circuit is one whose output does. Because computer memory requires data to be retained over time, it is inherently time-dependent, and must be built with sequential logic gates. The sequential circuitry used in the Nand2Tetris ‘Hack’ computer is called the data flip-flop, which “remembers” the bit (either 0 or 1) inputted in the previous time unit. Project Notes The following describes major ideas I considered while writing the HDL for the register, memory, and program counter chips specified in Project 03. NOTE 12/13/23, revisiting Nand2Tetris: This section has been cut short since I finished this project in May 2023, but did not leave much commentary, nor do I remember much about the process of working on it. Mostly, I recall initially struggling to understand the function of a DFF gate in a way where I could manipulate it to construct the specified sequential chips. I also found the hint in the Nand2Tetris textbook about building larger RAM chips using recursion very helpful, so if you’re working on this project as well, I’d highly suggest you check that out. Don’t skip the textbook! Anyways, that’s it. I’m off to finish what I’d started on the next project.
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Nand2Tetris / Memory and Sequential Logic

03 May 2023

➤ NAND2TETRIS PROJECT 03

Concept Notes

A combinational circuit is one whose output does not depend on the value of the previous output, whereas a sequential circuit is one whose output does. Because computer memory requires data to be retained over time, it is inherently time-dependent, and must be built with sequential logic gates.

The sequential circuitry used in the Nand2Tetris ‘Hack’ computer is called the data flip-flop, which “remembers” the bit (either 0 or 1) inputted in the previous time unit.

Project Notes

The following describes major ideas I considered while writing the HDL for the register, memory, and program counter chips specified in Project 03.

NOTE 12/13/23, revisiting Nand2Tetris: This section has been cut short since I finished this project in May 2023, but did not leave much commentary, nor do I remember much about the process of working on it. Mostly, I recall initially struggling to understand the function of a DFF gate in a way where I could manipulate it to construct the specified sequential chips. I also found the hint in the Nand2Tetris textbook about building larger RAM chips using recursion very helpful, so if you’re working on this project as well, I’d highly suggest you check that out. Don’t skip the textbook! Anyways, that’s it. I’m off to finish what I’d started on the next project.