Building an incrementer, half adder, full adder, and ALU using the gates from the previous project.

Project specifications | My work

Concepts

Most computer systems represent signed integers using a method called 2’s complement, where, in a fixed number of bits, negative integers are represented using the negation of their absolute value plus 1. This method is convenient for a number of reasons:

• Negative integers can seamlessly be included in binary addition operations.
• There is only one possible representation of 0.
• The most significant bit of any integer indicates its sign (0 for positive integers, and 1 for negative integers).

The arithmetic logic unit (ALU) is a computer chip that performs arithmetic and bitwise operations on integers represented in 2’s complement.

Process

Definition of NAND

Briefly had this misconstrued while building FullAdder. NAND is NOT(A AND B), not (NOT A) AND (NOT B).

ALU in <20 lines of HDL?

(It’s stated in the course materials that the ALU can be specified in less than 20 lines of HDL, so I wanted to achieve that.)

I’d originally tried to “zero” inputs by AND’ing them with NOT zx (or for the y-input, NOT zy), but of course, ran into the “different bus widths” error. Then, it hit me that I could write a Mux16 with a=input, b=false, and sel=zx (or NOT zy, for the y-input). In general, I’d forgotten about some of the chips I’d previously built, and was stuck until it hit me that they existed.

I also found myself running into the “sub bus of an internal node” error several times while writing the HDL for detecting zero or negative outputs. It worked after some syntactical adjustments, though. I used two 8-way ORs, an OR, and a NOT to detect zeros, and simply outputted the “out” value’s most significant bit to detect negatives.

Ultimately, I ended up with a pretty clean 15 lines of HDL.

For Further Inquiry

Carry-lookahead Adder

I want to try building an adder that can detect whether a bit pair will generate or propagate a carry.